| File Name ↓ | File Size ↓ | Date ↓ |
|---|---|---|
| Parent directory/ | - | - |
| 01 - Introduction to the course/ | - | 2023-Nov-10 11:47 |
| 02 - Introduction to Verilog HDL/ | - | 2023-Nov-10 10:06 |
| 03 - VLSI design flow ( FPGA & ASIC)/ | - | 2023-Nov-10 11:47 |
| 04 - Three levels of verilog design Description/ | - | 2023-Nov-10 10:41 |
| 05 - Verilog Language constructs, Data types &..> | - | 2023-Nov-10 11:47 |
| 06 - Verilog Program structure/ | - | 2023-Nov-10 11:46 |
| 07 - Gate level modeling/ | - | 2023-Nov-10 11:47 |
| 08 - Data flow modeling/ | - | 2023-Nov-10 11:47 |
| 09 - Behavioral Modeling/ | - | 2023-Nov-10 11:47 |
| 10 - Switch level modeling/ | - | 2023-Nov-10 11:47 |
| 11 - Test bench/ | - | 2023-Nov-10 11:46 |
| 12 - Functions & Task and system tasks/ | - | 2023-Nov-10 11:46 |
| 13 - FSM/ | - | 2023-Nov-10 11:47 |
| 14 - Sequence detector using FSM with complete ..> | - | 2023-Nov-10 11:47 |
| 15 - Project 1 Memory controller/ | - | 2023-Nov-09 21:15 |
| 16 - Project 2 FIFO/ | - | 2023-Nov-10 11:47 |
| 17 - Project 3 Hamming code complete Design & ..> | - | 2023-Nov-10 11:47 |
| 18 - FPGA/ | - | 2023-Nov-10 09:50 |
C:\Users\{username}\AppData\Local\Microsoft\WindowsAppsPowerShell or CMDwget -rnp then paste in the link of the directory from the site and hit EnterC:\Users\{username}