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12 - 5. Action Time - Design a Stream Cypher.mp4112.9 MiB2023-Nov-10 08:53
12 - 3. Action Time - Data Transfer FSM.mp4108.8 MiB2023-Nov-10 08:52
11 - 3. Action Time - Special Semaphore (Mealy ..>103.0 MiB2023-Nov-10 08:53
12 - 2. Action Time - Synchronous FIFO.mp478.0 MiB2023-Nov-10 08:53
11 - 2. Action Time - Metro turnstile (Mealy FS..>70.0 MiB2023-Nov-10 08:53
9 - 14. Action Time - ALU self-checking testben..>59.4 MiB2023-Nov-10 08:51
10 - 2. Action Time - Single Port Async Read SR..>51.0 MiB2023-Nov-10 08:53
7 - 25. Action time - Design an Arithmetical Lo..>50.9 MiB2023-Nov-10 08:52
1 - 2. Course overview.mp450.5 MiB2023-Nov-10 08:53
10 - 4. Action Time - Dual Port Async Read SRAM..>49.9 MiB2023-Nov-10 08:45
1 - 1. Welcome!.mp443.6 MiB2023-Nov-10 08:53
8 - 7. Action Time - D_Flip_Flop_sync_rstn.mp442.1 MiB2023-Nov-10 08:52
8 - 14. Action Time - Shift_Reg_PISO.mp440.0 MiB2023-Nov-10 08:40
9 - 12. Action Time - Shift Reg PIPO buggy.mp439.8 MiB2023-Nov-10 08:51
8 - 17. Action Time - Linear Feedback Shift Reg..>39.0 MiB2023-Nov-10 08:53
8 - 15. Action Time - Shift_Left_Right_Reg.mp438.6 MiB2023-Nov-10 08:53
10 - 5. Action Time - Single Port Sync Read ROM..>37.7 MiB2023-Nov-10 08:52
8 - 20. Action Time - Nbit updown Counter.mp437.3 MiB2023-Nov-10 08:45
8 - 24. Action Time - Clock Divider by 3.mp436.7 MiB2023-Nov-10 08:53
5 - 6. Verilog_Behavioral_style.mp436.2 MiB2023-Nov-10 08:53
4 - 1. Verilog Module - the basics.mp434.9 MiB2023-Nov-10 08:41
5 - 15. Action Time - 4bit_full_adder structura..>34.1 MiB2023-Nov-10 08:53
11 - 1. Discover Finite State Machines.mp433.9 MiB2023-Nov-10 08:48
8 - 12. Action Time - Shift_Reg_SIPO.mp433.6 MiB2023-Nov-10 08:53
7 - 23. Action Time - HEX 7segment decoder.mp432.2 MiB2023-Nov-10 08:52
8 - 21. Action Time - Modulo_N Counter.mp432.1 MiB2023-Nov-10 08:52
11 - 5. Action Time - Sequence Detector NON Ove..>30.9 MiB2023-Nov-10 08:53
1 - 4. Understand Abstraction Levels.mp430.6 MiB2023-Nov-10 08:53
8 - 2. Action Time - Clocks Generator.mp429.2 MiB2023-Nov-10 08:52
4 - 2. Action time - Do your first testbench.mp429.2 MiB2023-Nov-10 08:51
7 - 21. Action Time - demux_4x_nbit.mp429.1 MiB2023-Nov-10 08:53
7 - 13. Action Time - 4to16 binary Decoder.mp428.7 MiB2023-Nov-10 08:53
9 - 7. Action Time - Nbit Comparator Function.mp428.2 MiB2023-Nov-10 08:51
11 - 7. Verilog Mealy FSM Template.mp428.1 MiB2023-Nov-10 08:51
8 - 6. Basics of edge-triggered logic.mp427.9 MiB2023-Nov-10 08:43
10 - 1. Basics of Semiconductor Memory.mp426.8 MiB2023-Nov-10 08:50
8 - 11. Action Time - Shift_Reg_PIPO.mp425.8 MiB2023-Nov-10 08:51
12 - 4. Basics of Data Ecryption.mp425.6 MiB2023-Nov-10 08:53
8 - 1. Sequential Logic Basics.mp425.4 MiB2023-Nov-10 08:53
7 - 22. Master the Seven Segment Display Decode..>25.3 MiB2023-Nov-10 08:51
10 - 3. Action Time - Single Port Sync Read SRA..>24.8 MiB2023-Nov-10 08:50
8 - 19. Action Time - Nbit Counter.mp423.4 MiB2023-Nov-10 08:53
7 - 14. Action Time - 8to3 Encoder.mp423.4 MiB2023-Nov-10 08:52
12 - 1. Discover the First In First Out (FIFO) ..>22.8 MiB2023-Nov-10 08:52
8 - 23. Action Time - Clock Divider Nbit.mp422.7 MiB2023-Nov-10 08:53
7 - 19. Action Time - mux_4x_nbit.mp422.7 MiB2023-Nov-10 08:44
7 - 9. Action Time - Nbit Comparator.mp422.6 MiB2023-Nov-10 08:52
7 - 11. Action Time - Nbit Decoder.mp422.5 MiB2023-Nov-10 08:13
3 - 8. Action time - Vectors.mp422.5 MiB2023-Nov-10 08:47
5 - 3. Action Time - half adder structural.mp422.5 MiB2023-Nov-10 08:50
6 - 4. Discover the Multiplexer.mp422.4 MiB2023-Nov-10 08:53
8 - 10. Discover the Shift Register.mp422.4 MiB2023-Nov-10 08:53
7 - 8. Action Time - Nbit Adder.mp422.2 MiB2023-Nov-10 08:53
9 - 1. Verilog Functions Basics.mp421.5 MiB2023-Nov-10 08:53
1 - 5. Discover the Modern Digital Design Flow.mp421.2 MiB2023-Nov-10 08:17
6 - 13. Action Time - 1bit_comparator.mp420.7 MiB2023-Nov-10 08:53
8 - 13. Action Time - Shift_Reg_SISO.mp420.3 MiB2023-Nov-10 08:49
7 - 24. How to use digital logic for arithmetic..>20.3 MiB2023-Nov-10 08:49
8 - 18. Discover Synchronous Counters.mp420.0 MiB2023-Nov-10 08:28
2 - 2. Install Intel Quartus Prime Lite and Mod..>19.9 MiB2023-Nov-10 08:51
9 - 13. Discover Automated Verification.mp419.9 MiB2023-Nov-10 08:52
7 - 4. Action Time - Adder Tree.mp419.7 MiB2023-Nov-10 08:37
8 - 22. Discover Digital Frequency Dividers.mp419.5 MiB2023-Nov-10 08:51
7 - 1. What is Combinational logic.mp419.4 MiB2023-Nov-10 08:53
3 - 6. Action time - Literal values.mp419.3 MiB2023-Nov-10 08:48
7 - 5. Discover Procedural Assignments.mp419.1 MiB2023-Nov-10 08:47
9 - 10. Action Time - Verilog Tasks Control Shi..>19.0 MiB2023-Nov-10 08:45
8 - 3. Types of Sequential Digital Logic.mp419.0 MiB2023-Nov-10 08:53
6 - 7. Action Time -1bit_demux.mp418.9 MiB2023-Nov-10 08:53
6 - 2. Verilog Built-in_Primitives.mp418.9 MiB2023-Nov-10 08:53
5 - 13. Action Time - full_adder behavioral.mp418.7 MiB2023-Nov-10 08:46
2 - 3. Action Time - Hello World using Verilog.mp418.5 MiB2023-Nov-10 08:37
5 - 5. Action Time - half_adder dataflow.mp418.3 MiB2023-Nov-10 08:52
7 - 17. Action Time - Priority Encoder2 4to2.mp418.0 MiB2023-Nov-10 08:36
5 - 11. Action Time - full_adder structural.mp417.9 MiB2023-Nov-10 08:39
7 - 16. Action Time - Priority Encoder1 4to2.mp417.9 MiB2023-Nov-10 08:52
2 - 1. Discover the Verilog Simulation.mp417.5 MiB2023-Nov-10 08:36
8 - 4. Action Time - The D_Latch.mp417.4 MiB2023-Nov-10 08:38
5 - 16. Action Time - 4bit_full_adder dataflow.mp417.3 MiB2023-Nov-10 08:49
1 - 3. What is Verilog HDL.mp417.3 MiB2023-Nov-10 08:53
3 - 4. Action time - Multiple procedures.mp417.2 MiB2023-Nov-10 08:46
7 - 15. What is a Priority Encoder.mp416.7 MiB2023-Nov-10 08:53
3 - 29. Action Time - Replication Operator.mp416.7 MiB2023-Nov-10 08:53
6 - 5. Action Time - 1bit_mux.mp416.6 MiB2023-Nov-10 08:49
8 - 5. Action Time - D_Latch_reset_n.mp416.5 MiB2023-Nov-10 08:25
12 - 6. Congratulations!.mp416.5 MiB2023-Nov-10 08:49
7 - 6. Action Time - Tree Adder Procedural.mp416.4 MiB2023-Nov-10 08:51
4 - 6. Action Time - Generate Waveforms.mp416.1 MiB2023-Nov-10 03:15
9 - 5. Action Time - Verilog Functions Factori..>15.7 MiB2023-Nov-10 08:53
3 - 3. Hardware Description Language data types..>15.7 MiB2023-Nov-10 08:53
8 - 8. Action Time - D_Flip_Flop_async_rstn.mp415.6 MiB2023-Nov-10 08:51
8 - 16. Discover the Linear Feedback Shift Regi..>15.5 MiB2023-Nov-10 08:52
6 - 6. Discover the Demultiplexer.mp415.4 MiB2023-Nov-10 08:52
7 - 10. Differentiate between binary encoders a..>15.4 MiB2023-Nov-10 08:30
3 - 1. Verilog Data types overview.mp415.4 MiB2023-Nov-10 08:42
9 - 4. Discover Verilog Recursive Functions.mp415.3 MiB2023-Nov-10 08:53
3 - 15. Action Time - Logical Operators usage.mp415.1 MiB2023-Nov-10 08:52
6 - 11. Action Time - mux_tri-state.mp415.0 MiB2023-Nov-10 08:53
3 - 2. Action time - sum and product.mp415.0 MiB2023-Nov-10 08:50
5 - 10. Design a 1bit full_adder.mp414.6 MiB2023-Nov-10 08:49
5 - 8. Action Time - Initial Procedures.mp414.4 MiB2023-Nov-10 08:07
7 - 3. Action Time - Continuous assignments.mp414.4 MiB2023-Nov-10 08:49
9 - 11. Why our code looks like software.mp414.3 MiB2023-Nov-10 08:52
3 - 12. Action Time - Reduction operators.mp414.1 MiB2023-Nov-10 08:43
3 - 27. Action Time - Concatenation Operator.mp413.8 MiB2023-Nov-10 08:47
3 - 10. Action Time - Bit-wise operators.mp413.6 MiB2023-Nov-10 08:25
5 - 1. What are HDL Design Styles.mp413.5 MiB2023-Nov-10 08:53
5 - 9. Action Time - half_adder behavioral.mp413.1 MiB2023-Nov-10 08:43
3 - 31. Action Time - Operators Precedence.mp412.6 MiB2023-Nov-10 08:49
9 - 2. Action Time - Verilog Functions1.mp412.6 MiB2023-Nov-10 08:16
3 - 5. What are Literal Values.mp412.3 MiB2023-Nov-10 03:31
3 - 25. Action Time - Conditional Operator.mp412.3 MiB2023-Nov-10 08:46
7 - 18. Discover bus Multiplexers.mp412.0 MiB2023-Nov-10 08:43
3 - 9. Verilog Operators - Bit-wise.mp412.0 MiB2023-Nov-10 03:33
11 - 6. Action Time - Sequence Detector Overlap..>11.9 MiB2023-Nov-10 03:00
3 - 18. Verilog Operators - Shift.mp411.7 MiB2023-Nov-10 08:38
3 - 19. Action Time - Shift Operators.mp411.6 MiB2023-Nov-10 08:50
8 - 9. Remember!.mp411.4 MiB2023-Nov-10 08:52
5 - 17. Action Time - 4bit_full_adder behaviora..>11.4 MiB2023-Nov-10 08:51
9 - 6. Action Time - Verilog Functions Fibonacc..>11.4 MiB2023-Nov-10 08:52
5 - 12. Action Time - full_adder dataflow.mp411.1 MiB2023-Nov-10 08:43
9 - 9. Action Time - Verilog Tasks Distance Con..>11.0 MiB2023-Nov-10 08:46
2 - 4. Congratulations!.mp410.9 MiB2023-Nov-10 08:40
7 - 2. Discover Continuous assignments.mp410.7 MiB2023-Nov-10 08:40
11 - 4. Basics of Sequence Detectors.mp410.5 MiB2023-Nov-10 08:18
6 - 9. Action Time - tri-state_buffer.mp410.5 MiB2023-Nov-10 08:48
3 - 21. Action Time - Relational Operators.mp410.5 MiB2023-Nov-10 08:52
3 - 7. Vectors in Verilog.mp410.5 MiB2023-Nov-10 08:32
4 - 5. Discover Time and Waveforms.mp410.2 MiB2023-Nov-10 08:49
5 - 2. Verilog Structural Design.mp410.2 MiB2023-Nov-10 08:53
9 - 3. Action Time - Verilog Functions2.mp410.2 MiB2023-Nov-10 08:50
3 - 14. Action Time - Logical Operators.mp410.1 MiB2023-Nov-10 08:12
3 - 22. Verilog Operators - Equality.mp410.0 MiB2023-Nov-10 08:52
9 - 8. Verilog Tasks Basics.mp410.0 MiB2023-Nov-10 08:52
6 - 3. Action Time - Built-in_gates.mp49.8 MiB2023-Nov-10 08:49
5 - 14. Design a 4bit full_adder.mp49.6 MiB2023-Nov-10 08:50
3 - 28. Verilog Operators - Replication.mp49.4 MiB2023-Nov-10 03:29
6 - 10. How to implement a multiplexer using tr..>9.4 MiB2023-Nov-10 08:53
7 - 12. How to use multiple binary decoders.mp49.2 MiB2023-Nov-10 08:53
6 - 1. What is Structural Design.mp49.2 MiB2023-Nov-10 08:47
4 - 4. What is a Testbench Architecture.mp49.2 MiB2023-Nov-10 08:51
7 - 20. Discover bus Demultiplexers.mp48.7 MiB2023-Nov-10 08:53
5 - 18. Congratulations!.mp48.6 MiB2023-Nov-10 08:32
6 - 8. The Tri-state buffer.mp48.4 MiB2023-Nov-10 08:47
6 - 14. Remember!.mp48.2 MiB2023-Nov-10 08:53
3 - 13. Verilog Operators - Logical.mp47.9 MiB2023-Nov-10 08:33
4 - 3. Remember!.mp47.6 MiB2023-Nov-10 08:52
3 - 17. Action Time - Arithmetic Operators.mp47.5 MiB2023-Nov-10 08:50
7 - 7. Discover the Nbit Adder.mp47.3 MiB2023-Nov-10 03:34
5 - 4. Verilog Dataflow style.mp47.3 MiB2023-Nov-10 08:41
7 - 26. Remember!.mp47.2 MiB2023-Nov-10 08:33
3 - 23. Action Time - Equality Operators.mp46.9 MiB2023-Nov-10 08:12
5 - 7. Remember!.mp46.9 MiB2023-Nov-10 08:26
3 - 24. Verilog Operators - Conditional.mp46.7 MiB2023-Nov-10 08:46
3 - 32. Congratulations!.mp46.4 MiB2023-Nov-10 08:53
3 - 26. Verilog Operators - Concatenation.mp46.3 MiB2023-Nov-10 08:52
3 - 20. Verilog Operators - Relational.mp46.3 MiB2023-Nov-10 03:24
6 - 12. Discover the 1bit Comparator.mp46.0 MiB2023-Nov-10 08:37
3 - 30. Verilog Operators - Precedence.mp44.9 MiB2023-Nov-10 08:33
3 - 11. Verilog Operators - Reduction.mp44.4 MiB2023-Nov-10 08:49
3 - 16. Verilog Operators - Arithmetic.mp43.7 MiB2023-Nov-10 08:36
12 - 5. Action Time - Design a Stream Cypher.srt14.5 KiB2023-Nov-10 08:37
12 - 3. Action Time - Data Transfer FSM.srt14.1 KiB2023-Nov-10 02:39
11 - 3. Action Time - Special Semaphore (Mealy ..>13.6 KiB2023-Nov-10 03:34
7 - 14.1 encoder_8to3.v11.4 KiB2023-Nov-10 03:34
8 - 11.1 shift_reg_pipo.v11.2 KiB2023-Nov-10 02:47
7 - 17.1 prio_enc2_4to2.v11.0 KiB2023-Nov-10 03:00
3 - 4.1 easy_verilog_example.v10.8 KiB2023-Nov-10 03:31
12 - 2. Action Time - Synchronous FIFO.srt10.5 KiB2023-Nov-10 03:01
11 - 2. Action Time - Metro turnstile (Mealy FS..>9.9 KiB2023-Nov-10 08:02
9 - 14.1 ALU.v7.0 KiB2023-Nov-10 02:42
9 - 14. Action Time - ALU self-checking testben..>6.7 KiB2023-Nov-10 02:42
7 - 25. Action time - Design an Arithmetical Lo..>6.6 KiB2023-Nov-10 08:18
10 - 4. Action Time - Dual Port Async Read SRAM..>6.6 KiB2023-Nov-10 08:12
10 - 2. Action Time - Single Port Async Read SR..>6.4 KiB2023-Nov-10 08:15
8 - 14. Action Time - Shift_Reg_PISO.srt5.9 KiB2023-Nov-10 08:19
8 - 7. Action Time - D_Flip_Flop_sync_rstn.srt5.7 KiB2023-Nov-10 08:15
8 - 17. Action Time - Linear Feedback Shift Reg..>5.2 KiB2023-Nov-10 08:27
8 - 15. Action Time - Shift_Left_Right_Reg.srt5.1 KiB2023-Nov-10 08:06
9 - 12. Action Time - Shift Reg PIPO buggy.srt5.1 KiB2023-Nov-10 08:12
1 - 2. Course overview.srt4.9 KiB2023-Nov-10 03:10
8 - 20. Action Time - Nbit updown Counter.srt4.8 KiB2023-Nov-10 03:14
10 - 5. Action Time - Single Port Sync Read ROM..>4.8 KiB2023-Nov-10 08:25
8 - 24. Action Time - Clock Divider by 3.srt4.7 KiB2023-Nov-10 08:53
10 - 4.1 ram_dp_async_read.v4.4 KiB2023-Nov-10 08:12
1 - 1. Welcome!.srt4.4 KiB2023-Nov-10 03:26
12 - 5.3 tb_encrypt.v4.3 KiB2023-Nov-10 08:37
11 - 1. Discover Finite State Machines.srt4.2 KiB2023-Nov-10 03:30
4 - 2. Action time - Do your first testbench.srt4.2 KiB2023-Nov-10 08:24
8 - 12. Action Time - Shift_Reg_SIPO.srt4.2 KiB2023-Nov-10 03:32
8 - 21. Action Time - Modulo_N Counter.srt4.1 KiB2023-Nov-10 08:23
4 - 1. Verilog Module - the basics.srt4.0 KiB2023-Nov-10 08:24
7 - 13. Action Time - 4to16 binary Decoder.srt4.0 KiB2023-Nov-10 03:08
11 - 5. Action Time - Sequence Detector NON Ove..>4.0 KiB2023-Nov-10 02:22
8 - 2. Action Time - Clocks Generator.srt3.9 KiB2023-Nov-10 08:41
5 - 15. Action Time - 4bit_full_adder structura..>3.8 KiB2023-Nov-10 08:08
5 - 6. Verilog_Behavioral_style.srt3.8 KiB2023-Nov-10 08:26
5 - 3. Action Time - half adder structural.srt3.7 KiB2023-Nov-10 02:56
11 - 3.1 semaphore_fsm.v3.7 KiB2023-Nov-10 03:34
9 - 7. Action Time - Nbit Comparator Function.srt3.7 KiB2023-Nov-10 03:35
2 - 3. Action Time - Hello World using Verilog.srt3.6 KiB2023-Nov-10 03:34
12 - 3.3 top_fsm.v3.6 KiB2023-Nov-10 02:39
8 - 11. Action Time - Shift_Reg_PIPO.srt3.5 KiB2023-Nov-10 02:47
12 - 2.1 fifo_sync.v3.5 KiB2023-Nov-10 03:01
10 - 3.1 ram_sp_sync_read.v3.5 KiB2023-Nov-10 08:04
7 - 14. Action Time - 8to3 Encoder.srt3.4 KiB2023-Nov-10 03:34
10 - 2.1 ram_sp_async_read.v3.4 KiB2023-Nov-10 08:15
7 - 21. Action Time - demux_4x_nbit.srt3.4 KiB2023-Nov-10 08:20
11 - 7. Verilog Mealy FSM Template.srt3.4 KiB2023-Nov-10 08:08
7 - 25.1 ALU.v3.3 KiB2023-Nov-10 08:18
8 - 6. Basics of edge-triggered logic.srt3.3 KiB2023-Nov-10 08:24
8 - 19. Action Time - Nbit Counter.srt3.3 KiB2023-Nov-10 08:10
1 - 4. Understand Abstraction Levels.srt3.3 KiB2023-Nov-10 03:29
8 - 23. Action Time - Clock Divider Nbit.srt3.2 KiB2023-Nov-10 08:05
12 - 4. Basics of Data Ecryption.srt3.2 KiB2023-Nov-10 08:43
7 - 8. Action Time - Nbit Adder.srt3.2 KiB2023-Nov-10 08:21
10 - 3. Action Time - Single Port Sync Read SRA..>3.2 KiB2023-Nov-10 08:04
7 - 23. Action Time - HEX 7segment decoder.srt3.2 KiB2023-Nov-10 03:25
1 - 5. Discover the Modern Digital Design Flow.srt3.1 KiB2023-Nov-10 08:08
7 - 9. Action Time - Nbit Comparator.srt3.0 KiB2023-Nov-10 03:04
12 - 3.2 tb_top_fsm.v3.0 KiB2023-Nov-10 02:39
11 - 2.1 fsm.v3.0 KiB2023-Nov-10 08:02
7 - 11. Action Time - Nbit Decoder.srt3.0 KiB2023-Nov-10 02:34
6 - 13. Action Time - 1bit_comparator.srt3.0 KiB2023-Nov-10 08:07
5 - 15.1 ripple_adder_4bit_structural.v2.9 KiB2023-Nov-10 08:08
7 - 19. Action Time - mux_4x_nbit.srt2.8 KiB2023-Nov-10 02:33
8 - 1. Sequential Logic Basics.srt2.7 KiB2023-Nov-10 02:35
7 - 4. Action Time - Adder Tree.srt2.7 KiB2023-Nov-10 02:59
7 - 22. Master the Seven Segment Display Decode..>2.6 KiB2023-Nov-10 03:13
8 - 13. Action Time - Shift_Reg_SISO.srt2.6 KiB2023-Nov-10 08:03
6 - 5. Action Time - 1bit_mux.srt2.6 KiB2023-Nov-10 08:03
6 - 7. Action Time -1bit_demux.srt2.6 KiB2023-Nov-10 03:16
3 - 8. Action time - Vectors.srt2.6 KiB2023-Nov-10 03:18
5 - 16.1 ripple_adder_4bit_dataflow.v2.5 KiB2023-Nov-10 02:24
5 - 5. Action Time - half_adder dataflow.srt2.5 KiB2023-Nov-10 08:51
10 - 1. Basics of Semiconductor Memory.srt2.5 KiB2023-Nov-10 08:04
9 - 13. Discover Automated Verification.srt2.5 KiB2023-Nov-10 03:07
5 - 11. Action Time - full_adder structural.srt2.5 KiB2023-Nov-10 08:04
9 - 12.1 shift_reg_pipo_buggy.v2.4 KiB2023-Nov-10 08:12
7 - 16. Action Time - Priority Encoder1 4to2.srt2.4 KiB2023-Nov-10 08:36
9 - 10. Action Time - Verilog Tasks Control Shi..>2.4 KiB2023-Nov-10 03:35
7 - 24. How to use digital logic for arithmetic..>2.4 KiB2023-Nov-10 02:30
6 - 11. Action Time - mux_tri-state.srt2.4 KiB2023-Nov-10 02:54
6 - 4. Discover the Multiplexer.srt2.4 KiB2023-Nov-10 02:52
3 - 2. Action time - sum and product.srt2.4 KiB2023-Nov-10 03:24
3 - 4. Action time - Multiple procedures.srt2.4 KiB2023-Nov-10 03:31
8 - 4. Action Time - The D_Latch.srt2.4 KiB2023-Nov-10 02:55
11 - 6.1 seq_det_overlap.v2.4 KiB2023-Nov-10 02:36
12 - 1. Discover the First In First Out (FIFO) ..>2.4 KiB2023-Nov-10 03:26
8 - 10. Discover the Shift Register.srt2.3 KiB2023-Nov-10 08:38
8 - 5. Action Time - D_Latch_reset_n.srt2.3 KiB2023-Nov-10 08:16
11 - 5.1 seq_det_non_overlap.v2.3 KiB2023-Nov-10 02:22
7 - 6. Action Time - Tree Adder Procedural.srt2.3 KiB2023-Nov-10 02:32
5 - 16. Action Time - 4bit_full_adder dataflow.srt2.2 KiB2023-Nov-10 02:24
8 - 18. Discover Synchronous Counters.srt2.2 KiB2023-Nov-10 03:29
7 - 3. Action Time - Continuous assignments.srt2.2 KiB2023-Nov-10 08:11
5 - 13. Action Time - full_adder behavioral.srt2.2 KiB2023-Nov-10 02:45
9 - 5. Action Time - Verilog Functions Factori..>2.2 KiB2023-Nov-10 03:08
7 - 17. Action Time - Priority Encoder2 4to2.srt2.1 KiB2023-Nov-10 03:00
9 - 1. Verilog Functions Basics.srt2.1 KiB2023-Nov-10 08:33
8 - 3. Types of Sequential Digital Logic.srt2.1 KiB2023-Nov-10 02:59
8 - 15.1 shift_left_right_load_reg.v2.1 KiB2023-Nov-10 08:06
8 - 20.1 counter_up_down_load_nbit.v2.1 KiB2023-Nov-10 03:14
3 - 6. Action time - Literal values.srt2.0 KiB2023-Nov-10 08:09
6 - 2. Verilog Built-in_Primitives.srt2.0 KiB2023-Nov-10 03:29
8 - 22. Discover Digital Frequency Dividers.srt2.0 KiB2023-Nov-10 02:31
7 - 1. What is Combinational logic.srt2.0 KiB2023-Nov-10 08:11
8 - 24.1 clock_div_3.v2.0 KiB2023-Nov-10 08:53
6 - 6. Discover the Demultiplexer.srt1.9 KiB2023-Nov-10 08:04
3 - 10. Action Time - Bit-wise operators.srt1.9 KiB2023-Nov-10 08:07
7 - 15. What is a Priority Encoder.srt1.9 KiB2023-Nov-10 02:45
8 - 8. Action Time - D_Flip_Flop_async_rstn.srt1.9 KiB2023-Nov-10 08:44
9 - 10.1 task_control_shift_reg.v1.9 KiB2023-Nov-10 03:35
2 - 2. Install Intel Quartus Prime Lite and Mod..>1.8 KiB2023-Nov-10 08:28
9 - 2. Action Time - Verilog Functions1.srt1.8 KiB2023-Nov-10 03:24
7 - 5. Discover Procedural Assignments.srt1.8 KiB2023-Nov-10 08:18
4 - 6. Action Time - Generate Waveforms.srt1.8 KiB2023-Nov-10 03:15
8 - 23.1 clock_div_nbit.v1.8 KiB2023-Nov-10 08:05
3 - 29. Action Time - Replication Operator.srt1.8 KiB2023-Nov-10 08:24
3 - 15. Action Time - Logical Operators usage.srt1.8 KiB2023-Nov-10 08:08
3 - 15.1 logical_operators_usage.v1.7 KiB2023-Nov-10 08:08
8 - 16. Discover the Linear Feedback Shift Regi..>1.7 KiB2023-Nov-10 03:20
5 - 11.1 full_adder_structural.v1.7 KiB2023-Nov-10 08:04
7 - 13.1 decoder_4to16.v1.7 KiB2023-Nov-10 03:08
7 - 10. Differentiate between binary encoders a..>1.7 KiB2023-Nov-10 02:18
3 - 12. Action Time - Reduction operators.srt1.7 KiB2023-Nov-10 08:32
3 - 27. Action Time - Concatenation Operator.srt1.7 KiB2023-Nov-10 03:24
7 - 23.1 hex_7seg_decoder.v1.7 KiB2023-Nov-10 03:25
5 - 8. Action Time - Initial Procedures.srt1.7 KiB2023-Nov-10 03:27
6 - 9. Action Time - tri-state_buffer.srt1.6 KiB2023-Nov-10 03:25
9 - 4. Discover Verilog Recursive Functions.srt1.6 KiB2023-Nov-10 08:39
5 - 10. Design a 1bit full_adder.srt1.6 KiB2023-Nov-10 08:16
1 - 3. What is Verilog HDL.srt1.6 KiB2023-Nov-10 08:27
10 - 5.2 rom.v1.6 KiB2023-Nov-10 08:25
3 - 3. Hardware Description Language data types..>1.6 KiB2023-Nov-10 08:21
3 - 9. Verilog Operators - Bit-wise.srt1.6 KiB2023-Nov-10 03:33
5 - 9. Action Time - half_adder behavioral.srt1.6 KiB2023-Nov-10 02:38
8 - 14.1 shift_reg_piso.v1.5 KiB2023-Nov-10 08:19
11 - 6. Action Time - Sequence Detector Overlap..>1.5 KiB2023-Nov-10 02:36
5 - 12. Action Time - full_adder dataflow.srt1.5 KiB2023-Nov-10 08:29
9 - 7.1 compare_nbit_func.v1.5 KiB2023-Nov-10 03:35
7 - 18. Discover bus Multiplexers.srt1.5 KiB2023-Nov-10 03:12
8 - 21.1 counter_modulo_n.v1.5 KiB2023-Nov-10 08:23
3 - 1. Verilog Data types overview.srt1.5 KiB2023-Nov-10 03:24
3 - 19. Action Time - Shift Operators.srt1.5 KiB2023-Nov-10 08:07
8 - 12.1 shift_reg_sipo.v1.5 KiB2023-Nov-10 03:32
2 - 1. Discover the Verilog Simulation.srt1.5 KiB2023-Nov-10 02:57
5 - 17. Action Time - 4bit_full_adder behaviora..>1.5 KiB2023-Nov-10 03:14
3 - 31. Action Time - Operators Precedence.srt1.4 KiB2023-Nov-10 08:07
7 - 6.1 adders3_procedural.v1.4 KiB2023-Nov-10 02:32
9 - 11. Why our code looks like software.srt1.4 KiB2023-Nov-10 02:33
9 - 9. Action Time - Verilog Tasks Distance Con..>1.4 KiB2023-Nov-10 08:46
8 - 13.1 shift_reg_siso.v1.4 KiB2023-Nov-10 08:03
7 - 19.1 mux_4x_nbit.v1.4 KiB2023-Nov-10 02:33
7 - 21.1 demux_nbit_x4.v1.4 KiB2023-Nov-10 08:20
9 - 6. Action Time - Verilog Functions Fibonacc..>1.3 KiB2023-Nov-10 02:32
5 - 12.1 full_adder_dataflow.v1.3 KiB2023-Nov-10 08:29
3 - 21. Action Time - Relational Operators.srt1.3 KiB2023-Nov-10 08:52
8 - 8.1 d_ff_async_rstn.v1.3 KiB2023-Nov-10 08:44
8 - 7.1 d_ff_sync_rstn.v1.3 KiB2023-Nov-10 08:15
3 - 25. Action Time - Conditional Operator.srt1.3 KiB2023-Nov-10 02:38
9 - 3. Action Time - Verilog Functions2.srt1.3 KiB2023-Nov-10 03:25
7 - 20. Discover bus Demultiplexers.srt1.3 KiB2023-Nov-10 08:09
5 - 2. Verilog Structural Design.srt1.3 KiB2023-Nov-10 08:50
8 - 17.1 lfsr_16.v1.3 KiB2023-Nov-10 08:27
3 - 17.1 math_operators.v1.2 KiB2023-Nov-10 08:15
4 - 4. What is a Testbench Architecture.srt1.2 KiB2023-Nov-10 03:21
7 - 9.1 comparator_nbit.v1.2 KiB2023-Nov-10 03:04
4 - 5. Discover Time and Waveforms.srt1.2 KiB2023-Nov-10 02:55
3 - 14. Action Time - Logical Operators.srt1.2 KiB2023-Nov-10 03:20
3 - 31.1 operators_precedence.v1.2 KiB2023-Nov-10 08:07
6 - 3. Action Time - Built-in_gates.srt1.2 KiB2023-Nov-10 08:49
3 - 14.1 logical_operators.v1.2 KiB2023-Nov-10 03:20
8 - 5.1 d_latch_rstn.v1.2 KiB2023-Nov-10 08:16
8 - 19.1 counter_nbit.v1.2 KiB2023-Nov-10 08:10
5 - 14. Design a 4bit full_adder.srt1.2 KiB2023-Nov-10 08:04
5 - 17.1 adder_4bit_behavioral.v1.2 KiB2023-Nov-10 03:14
2 - 4. Congratulations!.srt1.2 KiB2023-Nov-10 02:48
3 - 5. What are Literal Values.srt1.2 KiB2023-Nov-10 03:31
3 - 10.1 bitwise_operators.v1.2 KiB2023-Nov-10 08:07
5 - 1. What are HDL Design Styles.srt1.2 KiB2023-Nov-10 08:32
12 - 5.4 top_encrypt_golden.v1.2 KiB2023-Nov-10 08:37
6 - 10. How to implement a multiplexer using tr..>1.2 KiB2023-Nov-10 08:11
3 - 23.1 equality_operators.v1.2 KiB2023-Nov-10 08:07
7 - 16.1 prio_enc1_4to2.v1.1 KiB2023-Nov-10 08:36
3 - 22. Verilog Operators - Equality.srt1.1 KiB2023-Nov-10 02:46
9 - 8. Verilog Tasks Basics.srt1.1 KiB2023-Nov-10 08:04
3 - 18. Verilog Operators - Shift.srt1.1 KiB2023-Nov-10 08:38
7 - 2. Discover Continuous assignments.srt1.1 KiB2023-Nov-10 08:10
12 - 6. Congratulations!.srt1.1 KiB2023-Nov-10 08:17
5 - 8.1 procedures.v1.1 KiB2023-Nov-10 03:27
11 - 4. Basics of Sequence Detectors.srt1.1 KiB2023-Nov-10 03:30
7 - 4.1 adders3.v1.1 KiB2023-Nov-10 02:59
3 - 12.1 reduction_operators.v1.1 KiB2023-Nov-10 08:32
7 - 12. How to use multiple binary decoders.srt1.1 KiB2023-Nov-10 03:27
3 - 8.1 easy_vectors_example.v1.1 KiB2023-Nov-10 03:18
6 - 8. The Tri-state buffer.srt1.1 KiB2023-Nov-10 08:47
8 - 9. Remember!.srt1.0 KiB2023-Nov-10 08:14
8 - 4.1 d_latch.v1.0 KiB2023-Nov-10 02:55
3 - 7. Vectors in Verilog.srt1.0 KiB2023-Nov-10 02:49
3 - 28. Verilog Operators - Replication.srt1023 B2023-Nov-10 03:29
3 - 27.1 concatention_operator.v1015 B2023-Nov-10 03:24
6 - 1. What is Structural Design.srt1012 B2023-Nov-10 08:47
7 - 8.1 adder_nbit.v1004 B2023-Nov-10 08:21
12 - 5.5 top_encrypt.v990 B2023-Nov-10 08:37
7 - 11.1 decoder_nbit.v968 B2023-Nov-10 02:34
3 - 17. Action Time - Arithmetic Operators.srt948 B2023-Nov-10 08:15
5 - 3.1 half_adder_structural.v946 B2023-Nov-10 02:56
3 - 6.1 literal_values.v940 B2023-Nov-10 08:09
6 - 13.1 comparator_1bit.v936 B2023-Nov-10 08:07
3 - 13. Verilog Operators - Logical.srt933 B2023-Nov-10 08:12
5 - 9.1 half_adder_behavioral.v928 B2023-Nov-10 02:38
11 - 7.1 fsm_template.v911 B2023-Nov-10 08:08
5 - 5.1 half_adder_dataflow.v906 B2023-Nov-10 08:51
5 - 18. Congratulations!.srt866 B2023-Nov-10 08:14
8 - 2.1 clkgen.v857 B2023-Nov-10 08:41
3 - 19.1 shift_operators.v829 B2023-Nov-10 08:07
3 - 29.1 replication_operator.v828 B2023-Nov-10 08:24
9 - 9.1 task_meters_to_feet.v806 B2023-Nov-10 08:46
5 - 4. Verilog Dataflow style.srt799 B2023-Nov-10 03:03
6 - 11.1 mux_tristate.v784 B2023-Nov-10 02:54
3 - 11. Verilog Operators - Reduction.srt784 B2023-Nov-10 02:42
3 - 23. Action Time - Equality Operators.srt768 B2023-Nov-10 08:07
7 - 7. Discover the Nbit Adder.srt767 B2023-Nov-10 03:34
6 - 12. Discover the 1bit Comparator.srt766 B2023-Nov-10 08:22
7 - 3.1 some_logic.v762 B2023-Nov-10 08:11
4 - 2.2 my_first_testbench.v758 B2023-Nov-10 08:24
6 - 14. Remember!.srt728 B2023-Nov-10 08:49
3 - 32. Congratulations!.srt714 B2023-Nov-10 08:04
3 - 30. Verilog Operators - Precedence.srt709 B2023-Nov-10 08:33
3 - 26. Verilog Operators - Concatenation.srt704 B2023-Nov-10 08:16
9 - 6.1 function_ex4.v688 B2023-Nov-10 02:32
3 - 24. Verilog Operators - Conditional.srt671 B2023-Nov-10 08:46
6 - 3.1 built_in_gates.v667 B2023-Nov-10 08:49
4 - 3. Remember!.srt667 B2023-Nov-10 08:34
6 - 3.2 tb_gates.v661 B2023-Nov-10 08:49
3 - 25.1 conditional_operators.v648 B2023-Nov-10 02:38
9 - 5.1 function_ex3.v633 B2023-Nov-10 03:08
7 - 26. Remember!.srt628 B2023-Nov-10 08:18
5 - 7. Remember!.srt626 B2023-Nov-10 08:07
6 - 7.2 tb_demux.v623 B2023-Nov-10 03:16
3 - 20. Verilog Operators - Relational.srt618 B2023-Nov-10 03:11
12 - 3.1 ram_dp_async_read.v609 B2023-Nov-10 02:39
9 - 2.1 function_ex1.v588 B2023-Nov-10 03:24
12 - 5.1 prng.v570 B2023-Nov-10 08:37
9 - 3.1 function_ex2.v557 B2023-Nov-10 03:25
6 - 9.1 tb_tristate.v539 B2023-Nov-10 03:25
3 - 21.1 relational_operators.v507 B2023-Nov-10 08:52
6 - 5.2 tb_mux.v506 B2023-Nov-10 08:03
3 - 2.1 sum_product.v433 B2023-Nov-10 03:24
4 - 6.1 waveforms.v425 B2023-Nov-10 03:15
3 - 16. Verilog Operators - Arithmetic.srt413 B2023-Nov-10 08:09
6 - 5.1 mux_1bit.v271 B2023-Nov-10 08:03
6 - 7.1 demux_1bit.v224 B2023-Nov-10 03:16
2 - 3.1 hello_world.v208 B2023-Nov-10 03:34
6 - 9.2 tristate_buffer_1bit.v137 B2023-Nov-10 03:25
4 - 2.1 adder8bit.v133 B2023-Nov-10 08:24
12 - 5.2 secret_message.txt110 B2023-Nov-10 08:37
10 - 5.1 rom_init.hex66 B2023-Nov-10 08:25
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nginx/1.18.0 (Ubuntu)