\chapter{Memory Map}

\section{Overview}
The Hitachi 6309 CPU has 16 address lines and can thus address
2$^{16}$ = 65536 bytes which are 64 KB because $64 \times 1024 =
65536$.  The main memory RAM chip used inside the kolibri offers
512 KB of RAM addressed by 19 address lines. The same goes for
the Flash ROM chip. To address the whole amount of memory, way
more than the 64 KB the CPU is capable to address, a memory
management unit (MMU) is required. The kolibri uses a 74HCT612
chip for this purpose. It expands the 16 address lines of the
CPU to a total of 22 address lines, so a maximum of 2$^{22}$ = 4
MB can get addressed. This memory is split into pages of 16 KB
each, so four pages of 16 KB fit into the 64 KB address area of
the CPU.

The MMU is just a little more than a few bytes of RAM which hold
page numbers to define which 16 KB page shall appear at which of
the four 16 KB sections inside the total 64 KB the CPU can
access, so for example page 0 should appear at 0--16 KB, page 4
at 16--32 KB, page 5 at 32--48 KB and page 12 at 48--64 KB.

At the bottom and upper end of the 64 KB area, three fixed areas
are always visible:

The so called {\bf common RAM} area from 0--2 KB  always
accesses page 0, no matter which page is switched in for the
0--16 KB area.  The first 1024 bytes of this common RAM are used
by the operating system, the higher 1024 bytes are freely
available for the application.

At the upper end, the {\bf I/O area} is located from \$FE00 to
\$FEFF with a size of 256 bytes. About one fifth is used by
peripheral devices located on kolibri's main board, the rest is
available through the expansion port. The I/O area is always
visible, no matter of the MMU configuration.

To the very last, the topmost page from \$FF00 to \$FFFF is the
{\bf common ROM} which holds the reset and interrupt vectors
among other things. This common ROM is always visible, no matter
of the MMU configuration.

\section{MMU modes}
The MMU can either be switched on or off. The proper names for
these modes are {\bf pass mode} (MMU switched off) and map mode
(MMU switched on). Pass mode means that the MMU just passes
address lines A14 and A15 through from the CPU to the memory
chips and memory decoder, with all higher address lines starting
at A16 being held low. This is the default state after system
reset because the MMU's mapping RAM lacks a defined power-on
state and you won't have much luck with random garbage.

In pass mode, you have 32 KB RAM available at \$0000--\$7FFF and
32 KB ROM at \$8000--\$FFFF, of course minus the I/O area at
\$FE00--\$FEFF. Since the higher address lines are held low, the
visible 16 KB pages are taken from the lower end of the RAM and
ROM chips.

In {\bf map mode}, address lines A0--A13 are passed through and
the address lines A14 and A15 select one of four 16 KB pages,
defined by a byte stored in the MMU mapping RAM. The value of
this byte is used to define address lines MA14--MA21 which are
visible to the memory chips and memory decoder.

You might have noticed that A14 and A15 are mentioned in two
ways here: one from the CPU to select the 16 KB page and one
passed from the MMU to the memory. In order to be able to
distinguish them, the address lines which always attach directly
to the CPU are called A0--A14 and those mapped by the MMU are
called MA14--MA21, with the prefix 'M' indicating that they are
mapped by the MMU.

\section{Switching MMU configurations}
Different applications or routines may require different MMU
configurations, for example the application might handle large
arrays within a database, whereas the DOS routines need to
handle some file buffers. To fully define, which 16 KB page
should be visible in which 16 KB area, 4 bytes need to be
written to the MMU mapping RAM. It would be rather cumbersome if
every application would have to save and restore these four
bytes to switch the MMU configuration. That's why a shortcut
exists: any access to one of four I/O memory addresses selects
another MMU configuration.

It doesn't matter if you read or write to these addresses. The
value of written bytes is ignored, it's just the address that
matters.

Seen from a technical point of view, the state of address line
A0 is copied to the MMU configuration signal P0 and address line
A1 is copied to P1 when one of these locations is addressed.
These two lines P0 and P1 tell the MMU which memory mapping
shall be used.

\begin{verbatim}
   IO_MEMCONF0   $FE20   Memory configuration 0
   IO_MEMCONF1   $FE21   Memory configuration 1
   IO_MEMCONF2   $FE22   Memory configuration 2
   IO_MEMCONF3   $FE23   Memory configuration 3
\end{verbatim}

\section{Defining MMU configurations}
\begin{tabbing}
\$FFFF \= 0000 \=32--64 KB \= 3 \kill % just to define max width
\$FE00 \= 0000 \= 0--16 KB \= 3 \\
\$FE01 \= 0001 \= 0--16 KB \= 3 \\
\$FE02 \= 0010 \= 0--16 KB \= 3 \\
\$FE03 \= 0011 \= 0--16 KB \= 3 \\
\end{tabbing}

\section{Description of I/O area addresses}
TODO


