Setting log file to 'C:/Users/cameron/Projects/8-Bit-Adventures/lattice/MMU_1/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/ec.v'
Done: design load finished with (0) errors, and (0) warnings