TimeQuest Timing Analyzer report for z80mmu
Sun Feb 11 13:30:23 2024
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. Clocks
  5. Fmax Summary
  6. Setup Summary
  7. Hold Summary
  8. Recovery Summary
  9. Removal Summary
 10. Minimum Pulse Width Summary
 11. Setup: 'clk'
 12. Hold: 'clk'
 13. Minimum Pulse Width: 'clk'
 14. Setup Times
 15. Hold Times
 16. Clock to Output Times
 17. Minimum Clock to Output Times
 18. Setup Transfers
 19. Hold Transfers
 20. Report TCCS
 21. Report RSKM
 22. Unconstrained Paths
 23. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; z80mmu                                                            ;
; Device Family      ; MAX7000S                                                          ;
; Device Name        ; EPM7128SLC84-7                                                    ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Slow Model                                                        ;
; Rise/Fall Delays   ; Unavailable                                                       ;
+--------------------+-------------------------------------------------------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 16     ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                          ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; clk        ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk } ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+


+-------------------------------------------------+
; Fmax Summary                                    ;
+-----------+-----------------+------------+------+
; Fmax      ; Restricted Fmax ; Clock Name ; Note ;
+-----------+-----------------+------------+------+
; 125.0 MHz ; 125.0 MHz       ; clk        ;      ;
+-----------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------+
; Setup Summary                  ;
+-------+--------+---------------+
; Clock ; Slack  ; End Point TNS ;
+-------+--------+---------------+
; clk   ; -7.000 ; -35.000       ;
+-------+--------+---------------+


+-------------------------------+
; Hold Summary                  ;
+-------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+-------+---------------+
; clk   ; 3.000 ; 0.000         ;
+-------+-------+---------------+


--------------------
; Recovery Summary ;
--------------------
No paths to report.


-------------------
; Removal Summary ;
-------------------
No paths to report.


+--------------------------------+
; Minimum Pulse Width Summary    ;
+-------+--------+---------------+
; Clock ; Slack  ; End Point TNS ;
+-------+--------+---------------+
; clk   ; -2.500 ; -25.000       ;
+-------+--------+---------------+


+----------------------------------------------------------------------------------------------------------------------+
; Setup: 'clk'                                                                                                         ;
+--------+-------------------+-------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node           ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------+--------------+-------------+--------------+------------+------------+
; -7.000 ; rw~reg0           ; rw~reg0           ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
; -7.000 ; bank_register[1]  ; bank_register[1]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
; -7.000 ; bank_register[0]  ; bank_register[0]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
; -7.000 ; bank_register[2]  ; bank_register[2]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
; -7.000 ; addr_out[13]~reg0 ; addr_out[13]~reg0 ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
; -7.000 ; bank_register[2]  ; addr_out[13]~reg0 ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
; -7.000 ; bank_register[0]  ; addr_out[13]~reg0 ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
; -7.000 ; bank_register[1]  ; addr_out[13]~reg0 ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+--------+-------------------+-------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------+
; Hold: 'clk'                                                                                                         ;
+-------+-------------------+-------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node         ; To Node           ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------+--------------+-------------+--------------+------------+------------+
; 3.000 ; rw~reg0           ; rw~reg0           ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
; 3.000 ; bank_register[1]  ; bank_register[1]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
; 3.000 ; bank_register[0]  ; bank_register[0]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
; 3.000 ; bank_register[2]  ; bank_register[2]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
; 3.000 ; addr_out[13]~reg0 ; addr_out[13]~reg0 ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
; 3.000 ; bank_register[2]  ; addr_out[13]~reg0 ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
; 3.000 ; bank_register[0]  ; addr_out[13]~reg0 ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
; 3.000 ; bank_register[1]  ; addr_out[13]~reg0 ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+-------+-------------------+-------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------+
; Minimum Pulse Width: 'clk'                                                                              ;
+--------+--------------+----------------+------------------+-------+------------+------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                 ;
+--------+--------------+----------------+------------------+-------+------------+------------------------+
; -2.500 ; 0.500        ; 3.000          ; High Pulse Width ; clk   ; Rise       ; addr_out[13]~reg0      ;
; -2.500 ; 0.500        ; 3.000          ; Low Pulse Width  ; clk   ; Rise       ; addr_out[13]~reg0      ;
; -2.500 ; 0.500        ; 3.000          ; High Pulse Width ; clk   ; Rise       ; bank_register[0]       ;
; -2.500 ; 0.500        ; 3.000          ; Low Pulse Width  ; clk   ; Rise       ; bank_register[0]       ;
; -2.500 ; 0.500        ; 3.000          ; High Pulse Width ; clk   ; Rise       ; bank_register[1]       ;
; -2.500 ; 0.500        ; 3.000          ; Low Pulse Width  ; clk   ; Rise       ; bank_register[1]       ;
; -2.500 ; 0.500        ; 3.000          ; High Pulse Width ; clk   ; Rise       ; bank_register[2]       ;
; -2.500 ; 0.500        ; 3.000          ; Low Pulse Width  ; clk   ; Rise       ; bank_register[2]       ;
; -2.500 ; 0.500        ; 3.000          ; High Pulse Width ; clk   ; Rise       ; rw~reg0                ;
; -2.500 ; 0.500        ; 3.000          ; Low Pulse Width  ; clk   ; Rise       ; rw~reg0                ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; addr_out[13]~reg0|[17] ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; addr_out[13]~reg0|[17] ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; bank_register[0]|[18]  ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; bank_register[0]|[18]  ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; bank_register[1]|[18]  ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; bank_register[1]|[18]  ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; bank_register[2]|[18]  ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; bank_register[2]|[18]  ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk|dataout            ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk|dataout            ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; rw~reg0|[3]            ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; rw~reg0|[3]            ;
+--------+--------------+----------------+------------------+-------+------------+------------------------+


+--------------------------------------------------------------------------+
; Setup Times                                                              ;
+--------------+------------+-------+-------+------------+-----------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+--------------+------------+-------+-------+------------+-----------------+
; addr_in[*]   ; clk        ; 3.000 ; 3.000 ; Rise       ; clk             ;
;  addr_in[0]  ; clk        ; 3.000 ; 3.000 ; Rise       ; clk             ;
;  addr_in[1]  ; clk        ; 3.000 ; 3.000 ; Rise       ; clk             ;
;  addr_in[2]  ; clk        ; 3.000 ; 3.000 ; Rise       ; clk             ;
;  addr_in[3]  ; clk        ; 3.000 ; 3.000 ; Rise       ; clk             ;
;  addr_in[4]  ; clk        ; 3.000 ; 3.000 ; Rise       ; clk             ;
;  addr_in[5]  ; clk        ; 3.000 ; 3.000 ; Rise       ; clk             ;
;  addr_in[6]  ; clk        ; 3.000 ; 3.000 ; Rise       ; clk             ;
;  addr_in[7]  ; clk        ; 3.000 ; 3.000 ; Rise       ; clk             ;
;  addr_in[8]  ; clk        ; 3.000 ; 3.000 ; Rise       ; clk             ;
;  addr_in[9]  ; clk        ; 3.000 ; 3.000 ; Rise       ; clk             ;
;  addr_in[10] ; clk        ; 3.000 ; 3.000 ; Rise       ; clk             ;
;  addr_in[11] ; clk        ; 3.000 ; 3.000 ; Rise       ; clk             ;
;  addr_in[12] ; clk        ; 3.000 ; 3.000 ; Rise       ; clk             ;
;  addr_in[13] ; clk        ; 3.000 ; 3.000 ; Rise       ; clk             ;
;  addr_in[14] ; clk        ; 3.000 ; 3.000 ; Rise       ; clk             ;
;  addr_in[15] ; clk        ; 3.000 ; 3.000 ; Rise       ; clk             ;
; mem_req      ; clk        ; 3.000 ; 3.000 ; Rise       ; clk             ;
; read         ; clk        ; 3.000 ; 3.000 ; Rise       ; clk             ;
; write        ; clk        ; 3.000 ; 3.000 ; Rise       ; clk             ;
+--------------+------------+-------+-------+------------+-----------------+


+--------------------------------------------------------------------------+
; Hold Times                                                               ;
+--------------+------------+-------+-------+------------+-----------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+--------------+------------+-------+-------+------------+-----------------+
; addr_in[*]   ; clk        ; 2.000 ; 2.000 ; Rise       ; clk             ;
;  addr_in[0]  ; clk        ; 2.000 ; 2.000 ; Rise       ; clk             ;
;  addr_in[1]  ; clk        ; 2.000 ; 2.000 ; Rise       ; clk             ;
;  addr_in[2]  ; clk        ; 2.000 ; 2.000 ; Rise       ; clk             ;
;  addr_in[3]  ; clk        ; 2.000 ; 2.000 ; Rise       ; clk             ;
;  addr_in[4]  ; clk        ; 2.000 ; 2.000 ; Rise       ; clk             ;
;  addr_in[5]  ; clk        ; 2.000 ; 2.000 ; Rise       ; clk             ;
;  addr_in[6]  ; clk        ; 2.000 ; 2.000 ; Rise       ; clk             ;
;  addr_in[7]  ; clk        ; 2.000 ; 2.000 ; Rise       ; clk             ;
;  addr_in[8]  ; clk        ; 2.000 ; 2.000 ; Rise       ; clk             ;
;  addr_in[9]  ; clk        ; 2.000 ; 2.000 ; Rise       ; clk             ;
;  addr_in[10] ; clk        ; 2.000 ; 2.000 ; Rise       ; clk             ;
;  addr_in[11] ; clk        ; 2.000 ; 2.000 ; Rise       ; clk             ;
;  addr_in[12] ; clk        ; 2.000 ; 2.000 ; Rise       ; clk             ;
;  addr_in[13] ; clk        ; 2.000 ; 2.000 ; Rise       ; clk             ;
;  addr_in[14] ; clk        ; 2.000 ; 2.000 ; Rise       ; clk             ;
;  addr_in[15] ; clk        ; 2.000 ; 2.000 ; Rise       ; clk             ;
; mem_req      ; clk        ; 2.000 ; 2.000 ; Rise       ; clk             ;
; read         ; clk        ; 2.000 ; 2.000 ; Rise       ; clk             ;
; write        ; clk        ; 2.000 ; 2.000 ; Rise       ; clk             ;
+--------------+------------+-------+-------+------------+-----------------+


+---------------------------------------------------------------------------+
; Clock to Output Times                                                     ;
+---------------+------------+-------+-------+------------+-----------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+---------------+------------+-------+-------+------------+-----------------+
; addr_out[*]   ; clk        ; 7.500 ; 7.500 ; Rise       ; clk             ;
;  addr_out[13] ; clk        ; 7.500 ; 7.500 ; Rise       ; clk             ;
; rw            ; clk        ; 7.500 ; 7.500 ; Rise       ; clk             ;
+---------------+------------+-------+-------+------------+-----------------+


+---------------------------------------------------------------------------+
; Minimum Clock to Output Times                                             ;
+---------------+------------+-------+-------+------------+-----------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+---------------+------------+-------+-------+------------+-----------------+
; addr_out[*]   ; clk        ; 7.500 ; 7.500 ; Rise       ; clk             ;
;  addr_out[13] ; clk        ; 7.500 ; 7.500 ; Rise       ; clk             ;
; rw            ; clk        ; 7.500 ; 7.500 ; Rise       ; clk             ;
+---------------+------------+-------+-------+------------+-----------------+


+-------------------------------------------------------------------+
; Setup Transfers                                                   ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; clk        ; clk      ; 11       ; 0        ; 0        ; 0        ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------+
; Hold Transfers                                                    ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; clk        ; clk      ; 11       ; 0        ; 0        ; 0        ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 19    ; 19   ;
; Unconstrained Input Port Paths  ; 66    ; 66   ;
; Unconstrained Output Ports      ; 2     ; 2    ;
; Unconstrained Output Port Paths ; 2     ; 2    ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Sun Feb 11 13:30:22 2024
Info: Command: quartus_sta z80mmu -c z80mmu
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (306004): Started post-fitting delay annotation
Info (306005): Delay annotation completed successfully
Warning (335095): TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'z80mmu.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
    Info (332105): create_clock -period 1.000 -name clk clk
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -7.000
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -7.000       -35.000 clk 
Info (332146): Worst-case hold slack is 3.000
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     3.000         0.000 clk 
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -2.500
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -2.500       -25.000 clk 
Info (332001): The selected device family is not supported by the report_metastability command.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Peak virtual memory: 4505 megabytes
    Info: Processing ended: Sun Feb 11 13:30:23 2024
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01


