Analysis & Synthesis report for MemController
Thu Jan 18 18:23:52 2024
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. State Machine - |MemController|state
  9. Registers Removed During Synthesis
 10. Removed Registers Triggering Further Register Optimizations
 11. Parameter Settings for User Entity Instance: Top-level Entity: |MemController
 12. Analysis & Synthesis Messages
 13. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Jan 18 18:23:52 2024           ;
; Quartus II 64-Bit Version   ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name               ; MemController                                   ;
; Top-level Entity Name       ; MemController                                   ;
; Family                      ; MAX7000S                                        ;
; Total macrocells            ; 37                                              ;
; Total pins                  ; 51                                              ;
+-----------------------------+-------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                               ;
+----------------------------------------------------------------------------+----------------+---------------+
; Option                                                                     ; Setting        ; Default Value ;
+----------------------------------------------------------------------------+----------------+---------------+
; Device                                                                     ; EPM7128SLC84-7 ;               ;
; Top-level entity name                                                      ; MemController  ; MemController ;
; Family name                                                                ; MAX7000S       ; Cyclone IV GX ;
; Use smart compilation                                                      ; Off            ; Off           ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On             ; On            ;
; Enable compact report table                                                ; Off            ; Off           ;
; Create Debugging Nodes for IP Cores                                        ; Off            ; Off           ;
; Preserve fewer node names                                                  ; On             ; On            ;
; Disable OpenCore Plus hardware evaluation                                  ; Off            ; Off           ;
; Verilog Version                                                            ; Verilog_2001   ; Verilog_2001  ;
; VHDL Version                                                               ; VHDL_1993      ; VHDL_1993     ;
; State Machine Processing                                                   ; Auto           ; Auto          ;
; Safe State Machine                                                         ; Off            ; Off           ;
; Extract Verilog State Machines                                             ; On             ; On            ;
; Extract VHDL State Machines                                                ; On             ; On            ;
; Ignore Verilog initial constructs                                          ; Off            ; Off           ;
; Iteration limit for constant Verilog loops                                 ; 5000           ; 5000          ;
; Iteration limit for non-constant Verilog loops                             ; 250            ; 250           ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On             ; On            ;
; Infer RAMs from Raw Logic                                                  ; On             ; On            ;
; Parallel Synthesis                                                         ; On             ; On            ;
; NOT Gate Push-Back                                                         ; On             ; On            ;
; Power-Up Don't Care                                                        ; On             ; On            ;
; Remove Duplicate Registers                                                 ; On             ; On            ;
; Ignore CARRY Buffers                                                       ; Off            ; Off           ;
; Ignore CASCADE Buffers                                                     ; Off            ; Off           ;
; Ignore GLOBAL Buffers                                                      ; Off            ; Off           ;
; Ignore ROW GLOBAL Buffers                                                  ; Off            ; Off           ;
; Ignore LCELL Buffers                                                       ; Auto           ; Auto          ;
; Ignore SOFT Buffers                                                        ; Off            ; Off           ;
; Limit AHDL Integers to 32 Bits                                             ; Off            ; Off           ;
; Optimization Technique                                                     ; Speed          ; Speed         ;
; Allow XOR Gate Usage                                                       ; On             ; On            ;
; Auto Logic Cell Insertion                                                  ; On             ; On            ;
; Parallel Expander Chain Length                                             ; 4              ; 4             ;
; Auto Parallel Expanders                                                    ; On             ; On            ;
; Auto Open-Drain Pins                                                       ; On             ; On            ;
; Auto Resource Sharing                                                      ; Off            ; Off           ;
; Maximum Fan-in Per Macrocell                                               ; 100            ; 100           ;
; Use LogicLock Constraints during Resource Balancing                        ; On             ; On            ;
; Ignore translate_off and synthesis_off directives                          ; Off            ; Off           ;
; Report Parameter Settings                                                  ; On             ; On            ;
; Report Source Assignments                                                  ; On             ; On            ;
; Report Connectivity Checks                                                 ; On             ; On            ;
; HDL message level                                                          ; Level2         ; Level2        ;
; Suppress Register Optimization Related Messages                            ; Off            ; Off           ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000           ; 5000          ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000           ; 5000          ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100            ; 100           ;
; Block Design Naming                                                        ; Auto           ; Auto          ;
; Synthesis Effort                                                           ; Auto           ; Auto          ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On             ; On            ;
; Pre-Mapping Resynthesis Optimization                                       ; Off            ; Off           ;
; Analysis & Synthesis Message Level                                         ; Medium         ; Medium        ;
; Disable Register Merging Across Hierarchies                                ; Auto           ; Auto          ;
; Synthesis Seed                                                             ; 1              ; 1             ;
+----------------------------------------------------------------------------+----------------+---------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 16     ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                  ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                                    ; Library ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------+---------+
; MemController.v                  ; yes             ; User Verilog HDL File  ; C:/Users/cameron/Projects/8-Bit-Adventures/cpld_fpga/Altera/MMU/MemController.v ;         ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------+---------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 37                   ;
; Total registers      ; 9                    ;
; I/O pins             ; 51                   ;
; Parallel expanders   ; 1                    ;
; Maximum fan-out node ; clk                  ;
; Maximum fan-out      ; 9                    ;
; Total fan-out        ; 122                  ;
; Average fan-out      ; 1.39                 ;
+----------------------+----------------------+


+-------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                 ;
+----------------------------+------------+------+---------------------+--------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+------------+------+---------------------+--------------+
; |MemController             ; 37         ; 51   ; |MemController      ; work         ;
+----------------------------+------------+------+---------------------+--------------+


Encoding Type:  Minimal Bits
+--------------------------------------------------+
; State Machine - |MemController|state             ;
+----------+-------------------+-------------------+
; Name     ; state.state_bit_1 ; state.state_bit_0 ;
+----------+-------------------+-------------------+
; state.00 ; 0                 ; 0                 ;
; state.01 ; 1                 ; 0                 ;
; state.10 ; 1                 ; 1                 ;
; state.11 ; 0                 ; 1                 ;
+----------+-------------------+-------------------+


+--------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                   ;
+----------------------------------------+---------------------------------------------+
; Register name                          ; Reason for Removal                          ;
+----------------------------------------+---------------------------------------------+
; addr_out[14]~reg0                      ; Stuck at GND due to stuck port data_in      ;
; addr_out[15]~reg0                      ; Stuck at GND due to stuck port data_in      ;
; addr_out[16]~reg0                      ; Stuck at GND due to stuck port data_in      ;
; addr_out[17]~reg0                      ; Stuck at GND due to stuck port data_in      ;
; addr_out[18]~reg0                      ; Stuck at GND due to stuck port data_in      ;
; addr_out[19]~reg0                      ; Stuck at GND due to stuck port data_in      ;
; mem_err_int~reg0                       ; Stuck at GND due to stuck port data_in      ;
; intterupt_out_reg[0..5]                ; Stuck at GND due to stuck port data_in      ;
; bank_register[6,7]                     ; Stuck at GND due to stuck port data_in      ;
; state~0                                ; Lost fanout                                 ;
; data_bus[0]~reg0                       ; Stuck at GND due to stuck port data_in      ;
; data_bus[1]~reg0                       ; Stuck at GND due to stuck port data_in      ;
; data_bus[2]~reg0                       ; Stuck at GND due to stuck port data_in      ;
; data_bus[3]~reg0                       ; Stuck at GND due to stuck port data_in      ;
; data_bus[4]~reg0                       ; Stuck at GND due to stuck port data_in      ;
; data_bus[5]~reg0                       ; Stuck at GND due to stuck port data_in      ;
; bank_register[3..5]                    ; Stuck at GND due to stuck port data_in      ;
; intterupt_out_reg[7]                   ; Merged with intterupt_out_reg[6]            ;
; data_bus[7]~reg0                       ; Merged with data_bus[6]~reg0                ;
; bank_register[0..2]                    ; Stuck at VCC due to stuck port clock_enable ;
; Total Number of Removed Registers = 30 ;                                             ;
+----------------------------------------+---------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                              ;
+------------------+---------------------------+-------------------------------------------------------------------------------------------+
; Register name    ; Reason for Removal        ; Registers Removed due to This Register                                                    ;
+------------------+---------------------------+-------------------------------------------------------------------------------------------+
; mem_err_int~reg0 ; Stuck at GND              ; data_bus[0]~reg0, data_bus[1]~reg0, data_bus[2]~reg0, data_bus[3]~reg0, data_bus[4]~reg0, ;
;                  ; due to stuck port data_in ; data_bus[5]~reg0, bank_register[3], bank_register[4], bank_register[5], bank_register[2], ;
;                  ;                           ; bank_register[1], bank_register[0]                                                        ;
+------------------+---------------------------+-------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |MemController ;
+--------------------+------------------+---------------------------------------+
; Parameter Name     ; Value            ; Type                                  ;
+--------------------+------------------+---------------------------------------+
; BANK_0             ; 0000000          ; Unsigned Binary                       ;
; BANK_1             ; 0000001          ; Unsigned Binary                       ;
; BANK_2             ; 0000010          ; Unsigned Binary                       ;
; BANK_3             ; 0000011          ; Unsigned Binary                       ;
; BANK_4             ; 0000100          ; Unsigned Binary                       ;
; BANK_5             ; 0000101          ; Unsigned Binary                       ;
; BANK_6             ; 0000110          ; Unsigned Binary                       ;
; BANK_7             ; 0000111          ; Unsigned Binary                       ;
; WRITE_BANK_0       ; 1111111110100000 ; Unsigned Binary                       ;
; WRITE_BANK_1       ; 1111111110100001 ; Unsigned Binary                       ;
; WRITE_BANK_2       ; 1111111110100010 ; Unsigned Binary                       ;
; WRITE_BANK_3       ; 1111111110100011 ; Unsigned Binary                       ;
; WRITE_BANK_4       ; 1111111110100100 ; Unsigned Binary                       ;
; WRITE_BANK_5       ; 1111111110100101 ; Unsigned Binary                       ;
; WRITE_BANK_6       ; 1111111110100110 ; Unsigned Binary                       ;
; WRITE_BANK_7       ; 1111111110100111 ; Unsigned Binary                       ;
; IO_PROTECT_START   ; 1111110000000000 ; Unsigned Binary                       ;
; IO_PROTECT_END     ; 1111111011111111 ; Unsigned Binary                       ;
; INT_PAGE_PROTECTED ; 11000000         ; Unsigned Binary                       ;
; INT_PAGE_NOT_FOUND ; 11000001         ; Unsigned Binary                       ;
+--------------------+------------------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Thu Jan 18 18:23:52 2024
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MemController -c MemController
Warning (20028): Parallel compilation is not licensed and has been disabled
Warning (10229): Verilog HDL Expression warning at MemController.v(190): truncated literal to match 1 bits
Info (12021): Found 1 design units, including 1 entities, in source file memcontroller.v
    Info (12023): Found entity 1: MemController
Info (12127): Elaborating entity "MemController" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at MemController.v(239): object "bank_register" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at MemController.v(189): truncated value with size 8 to match size of target (1)
Warning (10027): Verilog HDL or VHDL warning at the MemController.v(199): index expression is not wide enough to address all of the elements in the array
Warning (10034): Output port "addr_out[12..0]" at MemController.v(12) has no driver
Warning (13034): The following nodes have both tri-state and non-tri-state drivers
    Warning (13035): Inserted always-enabled tri-state buffer between "data_bus[0]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "data_bus[1]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "data_bus[2]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "data_bus[3]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "data_bus[4]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "data_bus[5]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "data_bus[6]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "data_bus[7]" and its non-tri-state driver.
Warning (13050): Open-drain buffer(s) that do not directly drive top-level pin(s) are removed
    Warning (13051): Converted the fanout from the open-drain buffer "mem_err_int" to the node "mem_err_int" into a wire
Info (13060): One or more bidirs are fed by always enabled tri-state buffers
    Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidir "data_bus[0]" is moved to its source
    Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidir "data_bus[1]" is moved to its source
    Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidir "data_bus[2]" is moved to its source
    Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidir "data_bus[3]" is moved to its source
    Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidir "data_bus[4]" is moved to its source
    Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidir "data_bus[5]" is moved to its source
    Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidir "data_bus[6]" is moved to its source
    Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidir "data_bus[7]" is moved to its source
Warning (13009): TRI or OPNDRN buffers permanently enabled
    Warning (13010): Node "data_bus[0]~synth"
    Warning (13010): Node "data_bus[1]~synth"
    Warning (13010): Node "data_bus[2]~synth"
    Warning (13010): Node "data_bus[3]~synth"
    Warning (13010): Node "data_bus[4]~synth"
    Warning (13010): Node "data_bus[5]~synth"
    Warning (13010): Node "data_bus[6]~synth"
    Warning (13010): Node "data_bus[7]~synth"
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "addr_out[0]" is stuck at GND
    Warning (13410): Pin "addr_out[1]" is stuck at GND
    Warning (13410): Pin "addr_out[2]" is stuck at GND
    Warning (13410): Pin "addr_out[3]" is stuck at GND
    Warning (13410): Pin "addr_out[4]" is stuck at GND
    Warning (13410): Pin "addr_out[5]" is stuck at GND
    Warning (13410): Pin "addr_out[6]" is stuck at GND
    Warning (13410): Pin "addr_out[7]" is stuck at GND
    Warning (13410): Pin "addr_out[8]" is stuck at GND
    Warning (13410): Pin "addr_out[9]" is stuck at GND
    Warning (13410): Pin "addr_out[10]" is stuck at GND
    Warning (13410): Pin "addr_out[11]" is stuck at GND
    Warning (13410): Pin "addr_out[12]" is stuck at GND
    Warning (13410): Pin "addr_out[14]" is stuck at GND
    Warning (13410): Pin "addr_out[15]" is stuck at GND
    Warning (13410): Pin "addr_out[16]" is stuck at GND
    Warning (13410): Pin "addr_out[17]" is stuck at GND
    Warning (13410): Pin "addr_out[18]" is stuck at GND
    Warning (13410): Pin "addr_out[19]" is stuck at GND
Info (17049): 1 registers lost all their fanouts during netlist optimizations.
Warning (21074): Design contains 3 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "rw"
    Warning (15610): No output dependent on input pin "reset"
    Warning (15610): No output dependent on input pin "addr_in[0]"
Info (21057): Implemented 88 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 19 input pins
    Info (21059): Implemented 24 output pins
    Info (21060): Implemented 8 bidirectional pins
    Info (21063): Implemented 37 macrocells
Info (144001): Generated suppressed messages file C:/Users/cameron/Projects/8-Bit-Adventures/cpld_fpga/Altera/MMU/output_files/MemController.map.smsg
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 50 warnings
    Info: Peak virtual memory: 4563 megabytes
    Info: Processing ended: Thu Jan 18 18:23:52 2024
    Info: Elapsed time: 00:00:00
    Info: Total CPU time (on all processors): 00:00:01


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in C:/Users/cameron/Projects/8-Bit-Adventures/cpld_fpga/Altera/MMU/output_files/MemController.map.smsg.


