Design Assistant report for MemController
Sat Sep 16 17:03:17 2023
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


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; Table of Contents ;
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  1. Legal Notice
  2. Design Assistant Summary
  3. Design Assistant Settings
  4. Information only Violations
  5. Design Assistant Messages



----------------
; Legal Notice ;
----------------
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+-------------------------------------------------------------------------+
; Design Assistant Summary                                                ;
+-----------------------------------+-------------------------------------+
; Design Assistant Status           ; Analyzed - Sat Sep 16 17:03:17 2023 ;
; Revision Name                     ; MemController                       ;
; Top-level Entity Name             ; MemController                       ;
; Family                            ; MAX7000S                            ;
; Total Critical Violations         ; 0                                   ;
; Total High Violations             ; 0                                   ;
; Total Medium Violations           ; 0                                   ;
; Total Information only Violations ; 46                                  ;
; - Rule T102                       ; 46                                  ;
+-----------------------------------+-------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Design Assistant Settings                                                                                                                                                                                                                                                                                ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
; Option                                                                                                                                                                                                                                                                               ; Setting      ; To ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
; Design Assistant mode                                                                                                                                                                                                                                                                ; Post-Fitting ;    ;
; Threshold value for clock net not mapped to clock spines rule                                                                                                                                                                                                                        ; 25           ;    ;
; Minimum number of clock port feed by gated clocks                                                                                                                                                                                                                                    ; 30           ;    ;
; Minimum number of node fan-out                                                                                                                                                                                                                                                       ; 30           ;    ;
; Maximum number of nodes to report                                                                                                                                                                                                                                                    ; 50           ;    ;
; Rule C101: Gated clock should be implemented according to the Altera standard scheme                                                                                                                                                                                                 ; On           ;    ;
; Rule C102: Logic cell should not be used to generate an inverted clock signal                                                                                                                                                                                                        ; On           ;    ;
; Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power                                                                                                                                                                          ; On           ;    ;
; Rule C104: Clock signal source should drive only clock input ports                                                                                                                                                                                                                   ; On           ;    ;
; Rule C105: Clock signal should be a global signal (Rule applies during post-fitting analysis. This rule applies during both post-fitting analysis and post-synthesis analysis if the design targets a MAX 3000 or MAX 7000 device. For more information, see the Help for the rule.) ; On           ;    ;
; Rule C106: Clock signal source should not drive registers triggered by different clock edges                                                                                                                                                                                         ; On           ;    ;
; Rule R101: Combinational logic used as a reset signal should be synchronized                                                                                                                                                                                                         ; On           ;    ;
; Rule R102: External reset signals should be synchronized using two cascaded registers                                                                                                                                                                                                ; On           ;    ;
; Rule R103: External reset signal should be correctly synchronized                                                                                                                                                                                                                    ; On           ;    ;
; Rule R104: The reset signal that is generated in one clock domain and used in another clock domain should be correctly synchronized                                                                                                                                                  ; On           ;    ;
; Rule R105: The reset signal that is generated in one clock domain and used in another clock domain should be synchronized                                                                                                                                                            ; On           ;    ;
; Rule T101: Nodes with more than the specified number of fan-outs                                                                                                                                                                                                                     ; On           ;    ;
; Rule T102: Top nodes with the highest number of fan-outs                                                                                                                                                                                                                             ; On           ;    ;
; Rule A101: Design should not contain combinational loops                                                                                                                                                                                                                             ; On           ;    ;
; Rule A102: Register output should not drive its own control signal directly or through combinational logic                                                                                                                                                                           ; On           ;    ;
; Rule A103: Design should not contain delay chains                                                                                                                                                                                                                                    ; On           ;    ;
; Rule A104: Design should not contain ripple clock structures                                                                                                                                                                                                                         ; On           ;    ;
; Rule A105: Pulses should not be implemented asynchronously                                                                                                                                                                                                                           ; On           ;    ;
; Rule A106: Multiple pulses should not be generated in design                                                                                                                                                                                                                         ; On           ;    ;
; Rule A107: Design should not contain SR latches                                                                                                                                                                                                                                      ; On           ;    ;
; Rule A108: Design should not contain latches                                                                                                                                                                                                                                         ; On           ;    ;
; Rule S101: Output enable and input of the same tri-state node should not be driven by same signal source                                                                                                                                                                             ; On           ;    ;
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source                                                                                                                                                                ; On           ;    ;
; Rule S103: More than one asynchronous port of a register should not be driven by the same signal source                                                                                                                                                                              ; On           ;    ;
; Rule S104: Clock port and any other port of a register should not be driven by the same signal source                                                                                                                                                                                ; On           ;    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains                                                                                                                                                                                        ; On           ;    ;
; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain                                                                                                                 ; On           ;    ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains                                                                                                                                                                              ; On           ;    ;
; Rule M101: Data bits are not synchronized when transferred to the state machine of asynchronous clock domains                                                                                                                                                                        ; Off          ;    ;
; Rule M102: No reset signal defined to initialize the state machine                                                                                                                                                                                                                   ; Off          ;    ;
; Rule M103: State machine should not contain an unreachable state                                                                                                                                                                                                                     ; Off          ;    ;
; Rule M104: State machine should not contain a deadlock state                                                                                                                                                                                                                         ; Off          ;    ;
; Rule M105: State machine should not contain a dead transition                                                                                                                                                                                                                        ; Off          ;    ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+


+----------------------------------------------------------------------------------------+
; Information only Violations                                                            ;
+----------------------------------------------------------+-------------------+---------+
; Rule name                                                ; Name              ; Fan-Out ;
+----------------------------------------------------------+-------------------+---------+
; Rule T102: Top nodes with the highest number of fan-outs ; clk               ; 5       ;
; Rule T102: Top nodes with the highest number of fan-outs ; addr_in[9]        ; 5       ;
; Rule T102: Top nodes with the highest number of fan-outs ; addr_in[15]       ; 5       ;
; Rule T102: Top nodes with the highest number of fan-outs ; addr_in[12]       ; 5       ;
; Rule T102: Top nodes with the highest number of fan-outs ; addr_in[11]       ; 5       ;
; Rule T102: Top nodes with the highest number of fan-outs ; addr_in[10]       ; 5       ;
; Rule T102: Top nodes with the highest number of fan-outs ; addr_in[8]        ; 5       ;
; Rule T102: Top nodes with the highest number of fan-outs ; addr_in[14]       ; 5       ;
; Rule T102: Top nodes with the highest number of fan-outs ; addr_in[13]       ; 5       ;
; Rule T102: Top nodes with the highest number of fan-outs ; addr_in[6]        ; 4       ;
; Rule T102: Top nodes with the highest number of fan-outs ; addr_in[7]        ; 4       ;
; Rule T102: Top nodes with the highest number of fan-outs ; addr_in[3]        ; 4       ;
; Rule T102: Top nodes with the highest number of fan-outs ; addr_in[4]        ; 4       ;
; Rule T102: Top nodes with the highest number of fan-outs ; addr_in[5]        ; 4       ;
; Rule T102: Top nodes with the highest number of fan-outs ; mem_err_int~en    ; 3       ;
; Rule T102: Top nodes with the highest number of fan-outs ; data_bus[6]~reg0  ; 3       ;
; Rule T102: Top nodes with the highest number of fan-outs ; addr_in[2]        ; 2       ;
; Rule T102: Top nodes with the highest number of fan-outs ; addr_in[1]        ; 2       ;
; Rule T102: Top nodes with the highest number of fan-outs ; addr_out[13]~reg0 ; 2       ;
; Rule T102: Top nodes with the highest number of fan-outs ; intterupt_reg[6]  ; 2       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~2            ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~1            ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~0            ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~24           ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~16           ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~11           ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~14           ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~17           ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~15           ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~13           ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~18           ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~12           ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~10           ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~19           ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~9            ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~20           ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~21           ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~7            ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~6            ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~22           ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~8            ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~23           ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; io_select~reg0    ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~4            ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~3            ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND~5            ; 1       ;
+----------------------------------------------------------+-------------------+---------+


+---------------------------+
; Design Assistant Messages ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Design Assistant
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Sat Sep 16 17:03:17 2023
Info: Command: quartus_drc --read_settings_files=off --write_settings_files=off MemController -c MemController
Warning (335095): TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'MemController.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332144): No user constrained base clocks found in the design
Info (308044): (Information) Rule T102: Top nodes with the highest number of fan-outs. (Value defined:50). Found 46 node(s) with highest fan-out.
    Info (308011): Node  "clk"
    Info (308011): Node  "addr_in[9]"
    Info (308011): Node  "addr_in[15]"
    Info (308011): Node  "addr_in[12]"
    Info (308011): Node  "addr_in[11]"
    Info (308011): Node  "addr_in[10]"
    Info (308011): Node  "addr_in[8]"
    Info (308011): Node  "addr_in[14]"
    Info (308011): Node  "addr_in[13]"
    Info (308011): Node  "addr_in[6]"
    Info (308011): Node  "addr_in[7]"
    Info (308011): Node  "addr_in[3]"
    Info (308011): Node  "addr_in[4]"
    Info (308011): Node  "addr_in[5]"
    Info (308011): Node  "mem_err_int~en"
    Info (308011): Node  "data_bus[6]~reg0"
    Info (308011): Node  "addr_in[2]"
    Info (308011): Node  "addr_in[1]"
    Info (308011): Node  "addr_out[13]~reg0"
    Info (308011): Node  "intterupt_reg[6]"
    Info (308011): Node  "~GND~2"
    Info (308011): Node  "~GND~1"
    Info (308011): Node  "~GND~0"
    Info (308011): Node  "~GND~24"
    Info (308011): Node  "~GND~16"
    Info (308011): Node  "~GND~11"
    Info (308011): Node  "~GND~14"
    Info (308011): Node  "~GND~17"
    Info (308011): Node  "~GND~15"
    Info (308011): Node  "~GND~13"
    Info (308002): Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated.
Info (308007): Design Assistant information: finished post-fitting analysis of current design -- generated 46 information messages and 0 warning messages
Info: Quartus II 64-Bit Design Assistant was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 4491 megabytes
    Info: Processing ended: Sat Sep 16 17:03:18 2023
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:00


